FPGA ALU Design
Overview
This project focused on designing and deploying an Arithmetic Logic Unit (ALU) on a physical FPGA using the Digilent Basys3 development board. The ALU was written in SystemVerilog and synthesized using Vivado. It operates on two 4-bit inputs and supports several core arithmetic and logic operations, including addition, subtraction, bitwise OR, and bitwise AND.
The goal of the project was to move beyond simulation and verify that the hardware description could be successfully implemented on real hardware. User inputs were controlled through the Basys3 board’s onboard switches and push buttons, while outputs were displayed using the board’s LEDs. After synthesis, implementation, and bitstream generation, the design was programmed onto the FPGA and tested directly on the board.
Project Features
- Designed a 4-bit ALU using SystemVerilog
- Implemented arithmetic operations such as addition and subtraction
- Implemented logic operations such as bitwise AND and OR
- Used switches and buttons on the Basys3 board for user input
- Displayed output values using onboard LEDs
- Synthesized, implemented, and programmed the design using Vivado
- Verified the ALU through simulation and physical hardware testing
Basys3 Board
My Contributions
This project was completed as a two-person team. I contributed to the design, integration, testing, and debugging of the ALU system. My work involved helping develop the SystemVerilog modules, checking that the ALU operations produced the correct outputs, and verifying that the design worked correctly after being deployed to the Basys3 board.
I also helped debug issues that appeared during hardware testing. This included checking input mappings, validating output behavior, and making sure that the FPGA implementation matched the expected logic from the SystemVerilog design. Working with a teammate required clear communication and careful review of each part of the design so that the final system worked as intended.
What I Learned
This project gave me hands-on experience with the full FPGA development process, from writing HDL code to testing a working design on physical hardware. I learned how SystemVerilog modules are connected, synthesized, and translated into a real digital circuit on an FPGA.
I also gained a better understanding of the difference between software debugging and hardware debugging. Unlike normal software, FPGA designs require careful attention to signal behavior, timing, pin assignments, and physical board constraints. Testing the ALU on the Basys3 board helped reinforce how digital logic concepts are applied in real hardware.
Beyond the technical skills, this project also improved my ability to collaborate on a hardware design project. Since the system depended on multiple modules working together correctly, communication, testing, and peer review were important parts of the development process.