This project involved the design, implementation, and deployment of a SystemVerilog-based Arithmetic Logic Unit (ALU) on a physical FPGA using the Digilent Basys3 development board. The ALU operates on two 4-bit registers and supports core arithmetic and logic operations, including addition, subtraction, bitwise OR, and bitwise AND. The design was developed and synthesized using Vivado, with user interaction handled through onboard switches and push buttons, and outputs displayed on LEDs. Successful hardware testing confirmed correct real-time operation for all supported functions, demonstrating reliable translation from HDL design to physical FPGA implementation.
The project was completed as a two-person team, providing hands-on experience with collaborative hardware development and peer code review. Responsibilities were shared across module design, integration, testing, and debugging, requiring clear communication and iterative review of SystemVerilog code to ensure correctness and consistency across components. This collaboration strengthened skills in version-aware development, design validation, and teamwork, while reinforcing best practices for building and verifying modular digital systems in a real hardware environment.
Project Report: View full FPGA report (PDF)